Tous les appartements JA71. G. S. Lin and you will J. B. Kuo, “Fringing-Induced Slim-Channel-Impact (FINCE) Related Capacitance Choices regarding Nanometer FD SOI NMOS Equipment Using Mesa-Isolation Through 3d Simulation” , EDSM , Taiwan ,
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72. J. B. Kuo, “Advancement away from Bootstrap Techniques in Lower-Voltage CMOS Electronic VLSI Circuits to own SOC Applications” , IWSOC , Banff, Canada ,
P. Yang, “Gate Misalignment Perception Associated Capacitance Decisions away from an effective 100nm DG FD SOI NMOS Equipment that have n+/p+ Poly Better/Base Door” , ICSICT , Beijing, Asia
73. G. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Productive CMOS High-Stream Driver Circuit on Subservient Adiabatic/Bootstrap (CAB) Way of Low-Energy TFT-Liquid crystal display Program Programs” , ISCAS , Kobe, Japan ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and K. W. Su, “CGS Capacitance Trend out-of 100nm FD SOI CMOS Gadgets having HfO2 High-k Door Dielectric Provided Straight and Fringing Displacement Effects” , HKEDSSC , Hong kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Associated Capacitance Decisions regarding a beneficial 100nm DG SOI MOS Products having Letter+/p+ Top/Bottom Gate” , HKEDSSC , Hong kong ,
76. Grams. Y. Liu, Letter. C. Wang and you can J. B. Kuo, “Energy-Successful CMOS Higher-Weight Driver Circuit on the Complementary Adiabatic/Bootstrap (CAB) Way of Low-Electricity TFT-Lcd Program Software” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and you may J. B. Kuo, “A 0.8V CMOS TSPC Adiabatic DCVS Reasoning Circuit to your Bootstrap Strategy to possess Lower-Electricity VLSI” , ICECS , Israel ,
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80. J. B. Kuo and you will H. P. Chen, “A minimal-Current CMOS Load Rider into Adiabatic and you may Bootstrap Tricks for Low-Power Program Programs” , MWSCAS , Hiroshima, The japanese ,
83. Yards. T. Lin, Elizabeth. C. Sunshine, and you can J. B. Kuo, “Asymmetric Door Misalignment Impact on Subthreshold Characteristics DG SOI NMOS Products Provided Fringing Electronic Field effect” , Electron Products and you can Situation Symposium ,
84. J. B. Kuo, Elizabeth. C. Sun, and you may Meters. T. Lin, “Studies from Door Misalignment Effect on new Threshold Voltage away from Twice-Entrance (DG) Ultrathin FD SOI NMOS Equipment Playing with a concise Design Offered Fringing Digital Field-effect” , IEEE Electron Equipment to possess Microwave and you may Optoelectronic Applications ,
86. Age. Shen and you may J. 8V BP-DTMOS Blogs Addressable Memories Telephone Circuit Produced by SOI-DTMOS Processes” , IEEE Meeting towards Electron Equipment and Solid-state Circuits , Hong kong ,
87. P. C. Chen and you will J. B. Kuo, “ic Reasoning Routine Using a primary Bootstrap (DB) Way of Low-voltage CMOS VLSI” , Around the globe Symposium on the Circuits and you will Solutions ,
89. J. B. Kuo and you can S. C. Lin, “Lightweight Breakdown Design having PD SOI NMOS Gizmos Offered BJT/MOS Effect Ionization to possess Spice Circuits Simulation” , IEDMS , Taipei ,
ninety. J. B. Kuo and you may S. C. Lin, “Compact LDD/FD SOI CMOS Tool Model Provided Opportunity Transportation and you may Mind Temperature getting Liven Circuit Simulation” , IEDMS , Taipei ,
91. S. C. Lin and you will J. B. Kuo, “Fringing-Created Hindrance Lowering (FIBL) Ramifications of 100nm FD SOI NMOS Gizmos with a high Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Meeting Proc , Williamsburg ,
ninety-five. J. B. Kuo and you will S. C. Lin, “New Fringing Electronic Field effect towards Small-Channel Impression Tolerance Voltage away from FD SOI NMOS Gadgets having LDD/Sidewall Oxide Spacer Design” , Hong-kong Electron Equipment Fulfilling ,
93. C. L. Yang and you can J. B. Kuo, “High-Heat Quasi-Saturation Model of High-Current DMOS Power Devices” , Hong-kong Electron Devices Appointment ,
94. Elizabeth. Shen and you can J. B. Kuo, “0.8V CMOS Stuff-Addressable-Memories (CAM) Cellphone Ciurcuit which have an instant Level-Contrast Effectiveness Playing with Vast majority PMOS Active-Threshold (BP-DTMOS) Techniques Centered on Fundamental CMOS Technology having Lower-Voltage VLSI Options” , Globally Symposium towards the Circuits and you will Assistance (ISCAS) Proceedings , Arizona ,
